The present invention relates to the field of computing devices, and more particularly to the boot up of small, portable computing devices such as personal digital assistants and cell phones.
Portable electronic computing systems have evolved over the years from ROMized embedded systems with a small amount of RAM to the now conventional flash and RAM based systems that more resemble general purpose computing systems, having the ability to store and execute various application programs. The conventional three main factors considered in the design of these systems are cost, size, and power consumption. In recent years, the desire to load and execute application programs and other functions has driven the design towards a general operating system with ability to operate web browsers, portable code such as Java™, and other applications. A Java operating environment for such devices has been standardized, and is known as Java 2 Micro Edition (J2ME).
Presently, conventional small computing devices, including smart cellular phones, personal digital assistants (PDAs), and palm-top computers, use a non-volatile flash memory (NVM) to store a boot kernel and other operating system elements, application software, user interface (UI) elements, and data. This conventional NVM is typically NAND type memory, which makes it block-addressable, and not byte-addressable like RAM or standard ROM. It therefore requires a different bus. Upon start-up, the processor must load the operating kernel from the NVM into RAM, which is connected to the application processor by a separate bus. This arrangement causes a significant load time upon turning on a device before a user can start operating the device. User's notice the long “power up” time while they wait for the device to be ready to use after pressing the “on” button. This wait time can be somewhat annoying, and in emergency situations waiting up to a minute may be critical.
Prior to using NAND flash NVM, other arrangements were used, including ROM. However, ROM doesn't allow the device to be updated, or applications to be installed, so that approach has been discarded. A NOR memory type flash NVM has been used, which is byte-addressable, connected to the same bus as “pseudo-RAM.” Pseudo-RAM is a static RAM which is used for applications having low memory demand and which are not sophisticated systems. This arrangement allows “execute in place” (XIP) operation, but NOR type flash is significantly more expensive than NAND flash, and is not as durable (in lifetime write operations), so that approach also fell out of favor.
FIG. 1 shows a block schematic diagram 100 of an architecture for use in present conventional portable devices. A processor 102 is coupled to a NAND type flash NVM 104 via a first bus 106. The processor 102 is further coupled to a dynamic RAM (DRAM) 108 via a second bus 110. Upon powering up the device, the processor begins copying operating system and other instruction code from the flash to the DRAM, and indicated by arrow 112. Often the boot load copied to the DRAM is in compressed form to reduce memory footprint in the flash memory, thus requiring the boot kernel to be decompressed prior to instantiating it in the DRAM. This arrangement allows the device to have a general operating system to allow the addition of new application programs, as well as updates to the system software. It allows for use of less expensive NAND flash memory, as well as low cost DRAM type memory.
However, using two busses requires interface pins on the processor for each of the busses, causing the size of the processor integrated circuit to be larger than if just one bus were used. Additionally using two busses increases power consumption. Furthermore, while the block-addressable NAND flash is less expensive, having to copy from the flash, decompress the data, and copy it to the DRAM takes a substantial amount of time. Therefore there is a need for an architecture that eliminates a bus interface, and reduces the start up time upon powering up the device.